职位信息
职位名称	专业需求	薪资范围	招聘人数	工作地点	岗位职责	岗位类型
台积电2024届招聘简章	计算机科学与技术,电子信息	14000 - 25000	100	南京 上海	1)Develop SRAM/ROM compilers and customized macros. 2)Develop SRAM/ROM characterization flow and deliver design kits. 3)Develop Memory compiler tiling code.	正式岗位

招聘简章：

台积电2024届招聘简章

工作地点：上海/南京

台积电介绍 

1987年，台积公司成立于台湾新竹科学园区，并开创了专业集成电路制造服务商业模式。台积公司专注生产由客户所设计的芯片，本身并不设计、生产或销售自有品牌的芯片产品，确保绝不与客户竞争。而台积公司成功的关键，就在于协助客户获得成功。台积公司的专业集成电路制造服务商业模式造就了全球无晶圆厂IC设计产业的崛起。自创立以来，台积公司一直是世界领先的专业集成电路制造服务公司，2022年台积公司为532个客户提供服务，生产12,698种不同产品，被广泛地运用在各种终端市场，例如高效能运算、智能型手机、物联网、车用电子与消费性电子产品等；同时，台积公司及其子公司所拥有及管理的年产能超过一千五百万片十二吋晶圆约当量。

台积电（中国）有限公司介绍

台积电（中国）有限公司成立于2003年，位于上海市松江经济技术开发区内，是台积电独资设立的子公司，也是其全球布局中重要的一环。台积电（中国）面向国内客户，提供优质的生产、运筹及设计服务，生产8吋晶圆。其业务团队已遍布全国，在北京、深圳均有分公司，以增进客户在本土及全球半导体市场中的竞争力。

台积电（南京）有限公司介绍

台积电（南京）有限公司成立于2016年，位于南京浦口经济开发区，是台积电独资设立的子公司，生产12吋晶圆，同时成立南京设计服务中心，以最先进的芯片设计技术服务客户。台积电（南京）创造了台积很多新的里程碑，包含建厂速度最快、量产最快、获利最快。

校园招聘流程安排

【招聘流程】

网申 → 在线测评 → 初试、复试 → 录用通知 → 加入台积

【投递时间】

2023/8/18 - 2023/10/31

【投递方式】

手机端：

扫描下方二维码直接投递

上海职位	南京职位

 

在招职位

详情请参阅附件-职位介绍

晶彩台积

对台积人而言，生活的丰富和专业的成就同等重要；从食衣住行的满足到精神层面的提升，台积人在台积获得充分的保障。

这里拥有：

【六险一金缴纳】入职即缴纳社会保险及住房公积金，同时缴纳团体商业保险。

【房贷利息补贴】入职后在规定区域首次购房，符合条件即可申请按月领取利息补贴。

【员工持股计划】签订劳动合同次月即可参与购买股票，且公司提供购股补助金。

【餐厅用餐补贴】餐厅五餐供应（早、中、晚、夜宵和小早餐），除早餐外均可享餐补。

【员工宿舍小区】提供台积员工专属宿舍小区，设施完善，拎包即住。

【弹性假期制度】提供优于劳动法的休假制度，员工签订劳动合同满三个月即可享有。

【贴心工作环境】医、食、住、行、乐提供全方位的服务与设施，兼顾工作与生活。

这里更有：

完善的健身设施，贴心关怀的驻厂门诊，全天候的护理协助，免费年度健康检查服务，多条线路的交通班车，环保典范的工作环境是台积人享有的安心福利。

 

欢迎志同道合的您加入台积 一同释放全世界的创新！

职位介绍

1. IC设计工程师 （具体设计岗位如下）

1.1 SRAM design engineer（静态随机存储器设计工程师）（上海/南京）

岗位职责：

1)Develop SRAM/ROM compilers and customized macros.

2)Develop SRAM/ROM characterization flow and deliver design kits.

3)Develop Memory compiler tiling code.

任职资格：

1)Candidate must have a MS degree or above in Electrical or Computer Engineering

2)Knowledge on transistor level circuit design and layout design.

3)Experience in spice simulation or fast spice simulation.

4)Familiarity with Verilog and Synopsys .lib.

5)Ability in scripting language, such as Perl/Python/shell/tcl

1.2 Digital circuit design engineer（数字电路设计工程师）（上海/南京）

岗位职责：

1)Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)

2)Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)

任职资格：

1)Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.

2)Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred.

3)CAD and script capability such as Python/Perl/Shell is preferred.

4)Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.

5)Experience in reliability (EM, high-temperature aging effects, etc.) is a plus

6)Self-motivated and hard work.

1.3 IC Frontend design engineer（芯片前端设计工程师）（南京）

岗位职责：

1)RTL synthesis, SDC/UPF verification, low power design implementation for advanced technology chips.

2)Design flow/methodology development and innovation for front-end design challenges.

3)Be responsible for RTL verification, synthesis, low power design, and STA/timing closure works for customer’s projects and internal system test chips.

任职资格：

1)MS or above in EE, CS related fields. Experience in Digital IC design flow (from Synthesis, DFT, MBIST, Formality, STA), RTL design, RTL verification is plus.

2)New graduate or 3+ years working experience.

3)Familiar with EE CAD tool such as Design compiler, DFT complier, MBIST, n-Lint, Verdi, Verilog tools/flows.

4)Familiar with tcl/Perl/Python program.

1.4 IC Physical design engineer（芯片物理设计工程师）（南京）

岗位职责：

1)Physical implementation of advanced technology chips.

2)Design methodology development and innovation for advanced technology challenges.

3)Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.

4)Be responsible for advanced node PPA benchmark, and solution development.

5)EDA tool new features enablement.

6)Customer onsite/offsite supports will be required on demand.

任职资格：

1)MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.

2)New graduate or 3+ years working experience in chip physical implementation.

3)Familiar with Synopsys/Cadence APR tools/flows.

4)Familiar with TCL/Perl/Python programming.

5)Experience with TSMC advanced technology is plus.

6)Proven record in production tape-outs is plus.

6)Paper publication records

1.5 Layout Engineer（IP版图设计工程师）（上海）

岗位职责：

1)Full layout design for standard cell/IO/SRAM IPs in advanced process nodes

2)Work on the physical verification (DRC/LVS/Antenna ...)

3)Work on test chip layout design and verification

4)Close cooperation with designers on PPA optimization

任职资格：

1)At least BS Degree of Microelectronics or Physics.

2)Excellent graduate or at least 1 years' related working experience

3)Familiar with layout design and verification tools (Virtuoso, Laker, Calibre)

4)Familiar with design rule and layout effect in advanced process.

5)Excellent skills of communication and teamwork are also expected.

6)Programming experience (Perl/tcl skill) will be a plus.

7)Experience in advanced process (n16 and beyond) will be a plus.

1.6 DRC/LVS Development Engineer(DRC/LVS开发工程师）（上海/南京）

岗位职责：

1)Work closely with process RD team to develop DRC/LVS for design readiness.

2)Provide customer support to world-wide leading design house.

3)Initial more innovation to continue optimize development efficiency.

4)Work closely with various departments (Physical design/integration/Device RD/Product/ESD) on their design requirements.

5)Work closely with EDA partner for tool qualification and methodology enhance.

任职资格：

1)Good knowledge of semiconductor FEOL/BEOL process and chip design concepts. Solid understanding of device physics, Layout design is a plus.

2)Knowledge of EDA partner (Mentor, Synopsys, Cadence, etc.) tools suite is a plus. Especially Laker /Virtuoso /Calibre.

3)Scripting and programming experience using several of the following: Perl, Python, C, C++, TCL, Skill.

4)Ability to work across teams to drive a solution, problem solver and self-motivated.

5)The ideal candidate will have experience in DRC/LVS development.

6)MS or above in EE, CS related fields.

1.7 SPICE Modeling Engineer（上海）

岗位职责：

1)Test key design for SPICE modeling

2)SPICE model release for advanced and mainstream process

3)Device characterization

4)Customer support

5)Automation development on all SPICE modeling flow

任职资格：

1)Minimum MS degree majoring in EE, Physics or Engineering related fields.

2)Related experience in semiconductor device, measurement, extraction and SPICE simulation.

3)Proficiency in programming language, such as Perl or Python or C++ or VB.Net.

4)Must be effectively bilingual in Mandarin and English.

薪资福利：

对台积人而言，生活的丰富和专业的成就同等重要；从食衣住行的满足到精神层面的提升，台积人在台积获得充分的保障。

这里拥有：

【六险一金缴纳】入职即缴纳社会保险及住房公积金，同时缴纳团体商业保险。

【房贷利息补贴】入职后在规定区域首次购房，符合条件即可申请按月领取利息补贴。

【员工持股计划】签订劳动合同次月即可参与购买股票，且公司提供购股补助金。

【餐厅用餐补贴】餐厅五餐供应（早、中、晚、夜宵和小早餐），除早餐外均可享餐补。

【员工宿舍小区】提供台积员工专属宿舍小区，设施完善，拎包即住。

【弹性假期制度】提供优于劳动法的休假制度，员工签订劳动合同满三个月即可享有。

【贴心工作环境】医、食、住、行、乐提供全方位的服务与设施，兼顾工作与生活。

这里更有：

完善的健身设施，贴心关怀的驻厂门诊，全天候的护理协助，免费年度健康检查服务，多条线路的交通班车，环保典范的工作环境是台积人享有的安心福利。